Duty cycle control system

ABSTRACT

A closed loop control system for controlling the average output of a generator or other device. The output is detected and the detected signal is applied to a summing point at which it is summed with an externally supplied control signal. The summed signal is integrated and applied to a Schmidt Trigger, the output of which is coupled through control logic to control the generator. The generator duty cycle is controlled to maintain a desired average output. In a specific embodiment wherein the average output of a three phase converter supplying D.C. to the generator is controlled, at each duty cycle the converter is turned on at an initial reference potential crossing point and thereafter the output is a function of the difference between the most positive and the least positive phases.

Cox

Jan. 1, 1974 DUTY CYCLE CONTROL SYSTEM FOREIGN PATENTS OR APPLICATIONSInventor! Hamld C01, Richardson 66,215 9/1969 Germany 321/5 Tex.

[73] Assignee: Texas Instruments Incorporated, Primary Examiner-GraldGoldberg Dalas Att0rneyHarold Levme et a1.

[22] Filed: Aug. 13, 1971 57 ABSTRACT [21] A l, No,; 171,673 A closedloop control system for controlling the average output of a generator orother device. The output is detected and the detected signal is appliedto a sum- [52] US. Cl 321/5, 321/18, 321/440, ming point at which it issummed with an externally [51] I t Cl l supplied control signal. Thesummed signal is inte- [58] 18 2 grated and applied to a SchmidtTrigger, the output of 3 2 9 which is coupled through control logic tocontrol the generator. The generator duty cycle is controlled tomaintain a desired average output. In a specific em- [56] ReferencesC'ted bodiment wherein the average output of a three phase UNITED STATESPATENTS converter supplying DC. to the generator is con- 3,497,7942/1970 Fredrickson et a1 323/17 trolled, at each duty cycle theconverter is turned on 3,624,486 11/1971 O ates 321/18 at an initialreference potential crossing point and l Escher thereafter the output isa function of the difference ements 2,539,786 1/1951 Ussman 321/40 themost posmve and the least posmve pha 3,281,645 10/1965 Spink 321/473.465134 9/1969 Phadke 321/18 X 5 Claims, 9 Drawing Figures R.F. .1=.A.C.- CONTROL DETECTOR "GEN. 11c. LOGIC a3 3/ 2/ 29 V8 /5 II 25 2 7 v /3Z 0P 1 AMF! v S T V 4 C D PATENTEDJANZZ m4 3783; 366

sum 2 or 3 1 I x L A DUTY CYCLE 57 2 J F 'I LOAD OUTPUT PATENTED JAN 11974 SHEET 3 0F 3 DUTY CYCLE CONTROL SYSTEM This invention relatesgenerally to control systems and more particularly to control systemsfor controlling the duty cycle of devices which are alternately turnedon and off or otherwise alternately switched between two states.

One approach that has been used to control the duty cycle of deviceswhich must be alternately turned on and off for desired operation is toalternately turn the device on and off at predetermined intervals, asunder clock control. In thermal systems a common approach is to use athermostatic switch which turns the device off when a predeterminedmaximum level is reached and turns it back on again when a predeterminedminimum is reached. However, there is apparently no known closed loopcontrol system for controlling an average device output level bycontrolling the device duty cycle.

Accordingly, a specific embodiment of the invention comprises a closedloop control system for controlling the duty cycle of a radio frequencygenerator used for induction heating in a Czochralski crystal puller,thereby controlling the average generator output and maintaining thetemperature of the molten silicon constant as specified by a controlsignal. Changing the value of the control signal, e.g., under computercontrol, will change the average generator output and hence change themelt temperature.

The basic control system of this invention comprises a closed loopsystem wherein a control signal which indicates the desired averagegenerator output required to maintain a specified fixed melt temperatureis summed with the detected RF output of the generator, integrated andapplied to a Schmidt Trigger, the output of which is applied to controllogic which controls the AC-DC converter of the generator. The generatoris on only during the logic one output state of the Schmidt Trigger. Asthe logic state of the output of the Schmidt Trigger is dependent on themagnitude of the input waveform, the generator duty cycle is dependenton the integration of the summed control signal and detected actualgenerator output. Integration enables the desired average generatoroutput to be maintained, even though intermittent time delays may beincurred within the system. The closed loop system is immune from effectby power supply fluctuations and other external variables, and hencemaintains a stable, fixed output level while on, which in turn maintainsa stable desired melt temperature.

It is a significant feature of the control system of this invention thateach generator period is of a practically usable length regardless ofthe value of the desired duty cycle. According to some control schemes,the pulse width decreases as the duty cycle is decreased. Such a controlscheme cannot be utilized to control device (e.g., including heatinggenerator) for which both on and off periods must be of appreciablelength regardless of their relative proportions. Accordingly, in thesystem of this invention the device period is a usable minimum when theduty cycle is 0.5, and increases as the duty cycle approaches zero orone.

In a more specific aspect of the invention, the control logic controlsthe three phase converter power supply circuit of the generator tocontrol the supply voltage to the converter, and hence control thegenerator output. When the Schmidt Trigger output changes to a logicone, the converter is turned on only upon occurrence of an initial zerocrossing of two of the phases, thus avoiding the introduction of impulsefunctions on the system power lines. Thereafter the converter output isa function of the difference between the two phases having the largestand smallest potential, respectively until the Schmidt Trigger outputchanges to a logic zero and the generator is shut off.

It is a broad object of the invention to provide a closed loop controlsystem for controlling the duty cycle of a two-state device.

It is another object of the invention to provide a control system formaintaining a desired average output level of a generator.

It is another object of the invention to provide a control system formaintaining a desired average output level of a radio frequencygenerator powered by a three phase supply.

It is yet another object of the invention to provide a control systemfor maintaining a constant melt temperature in a Czochalski crystallpuller.

Other objects and advantages of the invention will become apparent fromthe following detailed description in conjunction with the drawings, inwhich:

FIG. 1 is a block diagram of a preferred control system;

FIGS. 2-4 are diagrams of signal waveforms from the system of FIG. 1;

FIG. 5 is a plot of pulse period as a function of the generator dutycycle;

FIG. 6 is a schematic diagram of the three phase converter power supplycircuit of the generator;

FIG. 7 is a signal waveform and level comparison of the supply phase;

FIG. 8 is a schematic diagram of the control logic; and

FIG. 9 is a schematic diagram of an RF detector.

A basic control system of this invention is illustrated in block diagramin FIG. 1. The closed control loop basically comprises a summing point17, an integrator 19, a Schmidt Trigger 25, control logic 29, radiofrequency (RF) generator 31 powered by a three phase AC-DC converter 30,and RF detector 33. This embodiment is employed to control the averageoutput of radio frequency generator of the type employed for RFinduction heating, as in Czochralski crystal pullers. It should beparticularly noted that the teachings of this specification are notlimited to the particular implementation disclosed.

The RF generator 31 is alternately turned on and off in order tomaintain a desired average output. The control system of FIG. 1 controlsthe generator duty cycle, i.e., the period of time during which thegenerator is on, in order to control the average generator output. Avoltage indicative of the desired average generator output is coupledtosumming point 17 through resistor 13. This voltage is summed with thedetected actual generator output, detected by RF detector 33, which iscoupled through resistor 15 to a summing point 17. The summed voltage isconnected as an input to integrator 19. The integrator 19 comprises anoperational amplifier having a capacitor 21 connected thereacross. Theoutput of the integrator 19 is connected by line 23 to a Schmidt Trigger25, the output of which is connected by line 27 to control logic 29.Control logic 29 alternately turns the converter of the RF generator onand off in order to provide the desired average output level.

The RF detector 33 continuously monitors the actual output level of RFgenerator 31.

It may be noted that in the control system of FIG. 1 the control loopmay be closed by applying the Schmidt Trigger output, or a calibratedfunction thereof, directly through the resistor to summing point 17, aswell as to control logic 29. In that arrangement of the RF detector33'is not required. However, such a system will not be immune from suchexternal variables as power supply fluctuations in the RF generatorcaused by line voltage variations. Thus a more stable generator outputis obtained by continuously detecting the actual output and applying thedetected output through resistor 15 to summing point 17.

Voltage V, is indicative of the desired average generator output level.As illustrated in FIG. 2, voltage V, is a d.c. voltage. The d.c. voltageV, may be changed at any given time in order to change the desiredaverage generator output, either by manual control or by computer underdirect digital control. The RF voltage output of the generator, which isdetected by RF detector 33, is indicated by waveform V in FIG. 2.Voltage V varies in a square wave relationship from zero potential to amaximum potential V,,,,. Thus the waveform V illustrated in FIG. 2indicates that the generator is on only during time period 1 During thistime period the input V of the Schmidt Trigger has a negative slope andits output V is at logic l At all times when the generator is on, theoutput level thereof is a d.c. voltage V,,,,. The control voltage V, isnegative with respect to the reference potential Output waveform V ofintegrator 19 is illustrated in the top portion of FIG. 3. Sawtoothwaveform V is input to a conventional Schmidt Trigger 25. A SchmidtTrigger has a logic output which is in either a logic one or logic zerostate at all times. The state of the output signal V of the SchmidtTrigger 25 depends on the magnitude of input waveform V The SchmidtTrigger 25 triggers when V peaks and thus, the output level of theSchmidt Trigger is a logic one while the slope of V is negative. Itagain triggers when V reaches a minimum, and thus the Schmidt Triggeroutput is a logical zero while the slope of V is positive.

The sawtooth shape of the input waveform to Schmidt Trigger 25 actuallyresults from the closed loop operation. A Schmidt Trigger produces alogic one when an upper trip point voltage is reached or surpassed, andproduces a logic zero when a lower trip point voltage is reached. Duringthe portion of a generator cycle when the generator is ofi, only thenegative control voltage appears at the integrator input, and thus theintegrator output is an increasing ramp. When this ramp reaches theupper trip point, the Schmidt Trigger is triggered to produce a logic 1,which turns the generator on. While the generator is on, the integratorinput is the net positive difference voltage between the positivegenerator output and the negative control voltage, and thus theintegrator output is a decreasing ramp. When this ramp decreases to thelower trip point, the Schmidt Trigger is triggered to produce a logic 0which turns the generator off.

The manner in which the duty cycle of the generator is controlled willnow be explained in more detail with reference to FIG. 4, whichillustrates an isolated pulse of the waveform V During the time periodt,, the RF generator output is zero and thus the only voltage present atthe input of integrator 19 is the negative d.c. voltage V Thus the slopeof the waveform V at the output of integrator 19 during this period isequal to the voltage V divided by the time constant RC of theintegrator, wherein resistor 13 and 15 are of value R and capacitor 21is of value C. Thus, the time period t, is given by the followingequation:

t, AVRC/V AVRC 11 a ....Vr 7 The duty cycle 1 during which the generatoris on is equal to time period divided by the total period t, of thepulse, which reduced to the following equation:

Thus, the duty cycle of the generator is equal to the ratio of thecontrol voltage V, to the peak generator output V FIG. 5 is a plotillustrating the period of the generator pulse as a function of the dutycycle. The abscissa in FIG. 5 is the duty cycle and the ordinate isactual time t normalized by the constant AVRClV The time periods t andt, are plotted for duty cycles of from zero to one. The sum of these twotime periods is the generator period and is represented by the curve t 2Thus, the period of each cycle of voltage V is a minimum when the dutycycle is 0.5 and increases as the duty cycle approaches zero or one. Theactual time value of the minimum period is a function of circuitconstants R and C, and can be increased by increasing the values of Rand C. Thus a usable period may be obtained for any value of duty cycle.

The power supply portion 30 of an RF generator 31 employed in anembodiment of this invention is illustrated in FIG. 6. A transformerhaving secondary windings 41, 43, 45 has primary windings (not shown)connected to the line voltage. Each of the phases A, B and C of thetransformer is coupled through a diode to the reference voltage. Eachphase is also connected to the anode of a thyratron, the cathodes ofwhich are coupled to supply power voltage to the generator designatedgenerally as load 59. Phase A is coupled through diode 42 to referencepotential 47; phase B is coupled through diode 44 to reference potential47; phase C is coupled through diode 46 to reference potential 47. PhaseA is coupled to the anode of thyratron 51; phase B is coupled to theanode of thyratron 53; phase C is coupled to the anode of thyratron 55.The center n of the Y-wound transformer is not connected to thereference potential.

The cathodes of all three thyratrons are connected to a common line 57,which carries the voltage furnished to the generator which in turndetermines the RF power supplied by the generator. The tyratronsbasically function as switches having an output which is a function ofthe input, but have a diode characteristic such that they are biased offin the reverse bias mode. After the generator is turned on, when thepotential of any one of the phases A, B or C becomes greater than theothers, the thyratrons connected to the other two phases are reversebiased off. Thus, the output on line 57 is determined by the mostpositive of the voltage phases at any given time. The most negative(i.e., least positive) of the phases A, B and C at any given time iscoupled to reference potential 47. Therefore, the voltage potentialsupplied to load 59 is the difference between the most positive phaseand the most negative phase at any given time.

Controlled operation of the RF generator is further illustrated inconnection with the timing diagram of FIG. 7. Sinusoidal waveforms A, Band C correspond to the respective voltages V V,, and V on the secondarywindings of the transformer of FIG. 6. The difference between the mostpositive and most negative phases, indicated by the dashed lines, is thesupply voltage furnished to the generator converter and is approximatelya d.c. voltage. In order to prevent the introduction of voltage spikesonthe power suppoy lines as the generator is turned on, turning on'of theconverter is synchronized to occur at zero crossing points (i.e.,reference potential crossing points) of two phases. Waveform 71 is alogical diagram of the function B-A 0. Similarly, waveform 72 is alogical diagram of the condition CB 0, and waveform 73 is a logicaldiagram of condition A -C 0. A logical 1 indicates that the condition istrue and a logical indicates that it is false. Prior to time point T3,the potential of phase B is more positive than phase A so that waveform71 is a logical I. At time point T the phase A potential becomes morepositive than the phase B potential and waveform 71 incurs a transitionto the logical 0 state. The transition from a logical 1 to a logical 0will be referred to hereinafter as a trailing pulse edge. Prior to timepoint T the potential of phase C is more positive than the potential ofphase A such that waveform 73 is in the logical 0 state. At time point Twaveform 73 undergoes a transition to a logical l state as a result ofthe waveform C potentialbecor nir ig less positive than potential A.Each transition from a logical 0 to a logical 1 will be referred tohereinafter as a leading pulse edge. Between time periods T and T thepotential of phase C is more positive than the potential of phase B andthus Waveform 72 is a logical 1. At time point T5, waveform 72 undergoesa transition to a 0 state as a result of waveform B becoming morepositive than C.

FIG. 8 is a schematic diagram of coiitrbiibgi iii."

Differential amplifier 81 has voltage phase C connected to the negativeinput and phase A connected to the positive input. Differentialamplifier 83 has phase A connected to the negative input and phase Bconnected to the positive input. Differential amplifier 85 has phase Bconnected to the negative input and phase C connected to the positiveinput. Each of the differential amplifiers 81, 83 and 85 areconventional operational amplifiers. The output of each of theseamplifiers (logic functions 71, 72, 73) is connected directly to aconventional one-shot multivibrator which provides a logic 1 output uponoccurrence of a positive-going waveform transition, or leading edge.Each output is also connected through an inverter to another one-shotmultivibrator to provide a logic 1" condition in response to occurrenceof a negative-going waveform transition, or trailing edge. Each of theone-shot multivibrators is of conventional design and goes to thelogical 1 condition for a short duration of time when triggered, andthen returns to the logical OZ condition again. All of the one-shortmultivibrators illustrated in FIG. 8 provide a logic 1 output when theinput waveform undergoes a transition from a logic 0 to a logic 1. Theoutput of differential amplifier 81 is coupled through a multivibrator94 to the input of NAND gate 104. The other input to NAND gate 104 isconnected to theUoutput of flip-flop 1 14. The output of differentialamplifier 81 is also coupled through inverter 97 and multivibrator 91 tothe input of NAND gate 101, the other input of which is connected to theoutput of AND gate 111. The output of differential amplifier 83 iscoupled through multivibrator to the input of NAND gate 105, the otherinput of which is connected to 6. The output of differential amplifier83 is also coupled through inverter 98 and multivibrator 92 to the inputof NAND g te 102, the other input of which is connected to the output ofAND gate 111. The output of differential amplifier 85 is coupled throughmultivibrator 96 to the input of NAND gate 106, the other input of whichis connected to 6. The output of differential amplifier 85 is alsocoupled through inverter 99 and multivibrator 93 to the input of NANDgate 103, the other input of which is coupled to the output of AND gate111. The output of NAND gate 104 is connected as an input to gate 121,the other input of which is connected to the output of gate 102. Theoutput of gate 105 is connected as an input to gate 122, the other inputof which is connected to the output of gate 103. The output of gate 106is connected as an input to gate 123, the other input of which isconnected to the output of gate 101. The output of gates 101, 102 and103 are all connected as inputs to NAND gate 115, the output of which isconnected to the reset input of flip-flop 114.

Operation of the logic circuit of FIG. 8 is initiated by receipt of alogic 1 condition of V the output of Schmidt Trigger 25, at AND gate111. When a logic 1 or run signal, is received, AND gate 111 has alreadybeen enabled as a result of the coupling of the trailing edge of theprior generator pulse signal through inverter 112 and multivibrator 113to the set input of flip-flop 114, thus applying a logic 1 condition Qinput qll fli 1 The output of NAND gate 121 is coupled to the grid ofthe thyratron 51, which has phase A coupled to its cathode. A logic 1output of gate 121 turns on, or fires, thyratron 51. Similarly, theoutputs of NAND gates 122 and 123 are coupled to fire phases B and C,respectively, 9191952195195,

Operation of the circuit of FIG. 8 will be explained in connection withthe timing diagram of FIG. 7. At time point T the condition of signal Vchanges from a logic 0 to a logic 1" (not specifically illustrated) as aresult of firing Schmidt Trigger 25. Since the Q output of flip-flop 114is already in the logical 1 condition, the output of AND gate 111changes to a logic l thus enabling gates 101, 102 and 103. Then, at timepoint T function CB 0 becomes true, corresponding to a leading edge ofthat signal. This leading edge triggers multivibrator 96, which appliesa logic 1 to the input of NAND gate 106. Since thefi output of flip-flop114 is at this time, flip-flop 106 is disabled. Thus, the generatorscannot be fired upon receipt of the initial leading edge. Then, at timepoint T signal B-A becomes less than zero. This trailing edge isinverted by inverter 98 and multivibrator 92 applies a logic 1 to NANDgate 102, which has been enabled by the logic l output of the AND gate111. The output of NAND gate 102 changes to a logic 0 and thus changesthe output of NAND gate 121 to a logic 1. This logic 1 signal is coupledto fire thyratron 51 by applying a bias to the grid thereof. In thismanner, the generator converter can be initially fired only by atrailing edge of one of the signals BA 0, CB 0 or AC 0. At time pointT.,, a leading edge of signal- AC 0 occurs. This leading edge causesmultivibrator 94 to apply to a logic 1 to NAND gate 104. Since the logic1 output of NAND gate 102 has changed the output of NAND gate 115 to alogic l the GOutput of flip-flop 114 is now a logic 1, and thus gate 104is enabled. A zero output of NAND gate 104 is applied to NAND gate 121so that the gate is disabled and the output remains a logic l and thusphase A continues to control the generator output. Simultaneously, the Qoutput of flip-flop 114 is changed to the logic 0 condition and thus theoutput of AND gate 111 is 0, disabling gates 101, 102 and 103. Afterthis point, only leadin'g edges will trigger the thyratrons during theremainder of the generator on time.

At time point T a leading edge of the signal BA 0 occurs. Thusmultivibrator 95 applies a logic 1 to NAND gate 105, the other input ofwhich has been enabled by 6. A logic 0 output of NAND gate 105 isapplied to NAND gate 122, changing the output thereof to a logic lthereby triggering thyratron 53. Thus at time point T phase B begins tocontrol the generator output. Thyratron 53 remains firing until timepoint T-, when the leading edge of signal CB 0 occurs. This leading edgetriggers multivibrator 96 to apply alogic 1 to NAND gate 106 and thus alogic 0 to NAND gate 123. A logic 1 output of NAND gate 123 then firesthyratron 55, which remains on until time point T In this manner, athyratron is initially fired upon occurrence of a first trailing edgeand thereafter the thyratrons are sequentially fired upon occurrence ofleading edges of the signals. By initiating generator converteroperation only with a trailing pulse edge, voltage impulses are notintroduced to the system power lines.

At the end of each generator on time the Schmidt Trigger output changesto a logic 0. This trailing pulse edge is coupled through inverter 112and multivibrator 113 to the set input of flip-flop 114, changing the Qoutput to a logic l Thus AND 111 is enabled for receipt of the next run"signal.

FIG. 9 is a schematic diagram of an RF detector employed in a preferredembodiment of the invention. The detector is basically a wire loopantenna twisted into a figure-eight configuration, forming equal loops151 and 153. The detector is placed adjacent to a conductor whichcouples the RF generator to the RF induction heating coils in aCzochralski crystal puller, with the conductor positioned on line 155through the center of the detector. The electric field from the conductor cuts the loops 151 and 153 in opposite directions, inducingvoltages which add together. Fields from conductors not equidistant fromthe two loops tend to cancel because they cut the loops in the samedirection.

The voltage induced across terminals 157 and 159 is rectified by diode161 to produce a d.c. voltage. The resulting d.c. voltage is smoothed bycapacitor 163. Shunt load resistor 165 limits the output acrossterminals167 and 169 to a desired calibration level at maximum RF. The output ofthe detector is applied to summing point 17.

Although the invention has been described in connection with a specificembodiment thereof, it is to be understood that the description hereinis intended only as illustrative.

What is claimed is:

1. Art on-off duty cycle control circuit for an electrical devicepowered by a d.c. voltage supply derived from a three-phase a.c. voltagesource through threeelement controlled rectifier devices each of whichhas an anode connected to one of said three-phase voltages, said circuitcomprising:

a. means generating a two level signal indicative of the on-off state ofthe electrical device to be controlled,

b. means generating a second signal of a magnitude indicative of thedesired on-off duty cycle of said electrical device,

c. means receiving said two level signal and said second signal andgenerating therefrom a summed signal,

d. means receiving said summed signal and generating an integratedsummed signal,

e. means receiving said integrated summed signal and generating independence of the magnitude and slope of said integrated summed signal acontrol signal of a first magnitude for an on period and of a secondmagnitude for the off period of said desired duty cycle,

f. means receiving said control signal and voltages from each of thethree phases of said a.c. source and generating during said on periodthree series of trigger pulses, each of said series for application tothe control electrode of a different one of said controlled rectifierdevices, each of said trigger pulses being timed to occur when the phasevoltage of the anode of the controlled rectifier to which said triggerpulse is to be applied becomes the most positive of the three phasevoltages of said a.c.

source.

2. A control circuit as defined in claim 1 wherein said last named meansfurther includes means generating an initial trigger pulse during eachof said on periods for application to the control electrode of the oneof said controlled rectifiers whose anode was at the reference voltageof said a.c. source at the beginning of said on period, said initialtrigger pulse being timed to occur as said anode becomes more positivethan said reference voltage.

3. In an on-off duty cycle control circuit for an electrical devicepowered by a d.c. power supply derived from a a.c. source having phasevoltage A, B and C through three-element controlled rectifier devices,each of which has an anode connected to one of said phase voltages, alogic circuit for triggering said controlled rectifier devicescomprising:

a. first, second and third comparator means, said first comparator meanshaving phases A and C as inb. first, second and third logic means havingan enable input and coupled to be responsive to leading edges of,respectively, the first, second and third square wave signals;

0. fourth, fifth and sixth logic means having an enable input andcoupled to be responsive to trailing edges of, respectively, the first,second and third square wave signals;

d. seventh logic means coupled to the output of said first logic meansand to the output of said fifth logic means, the output of said seventhlogic means being coupled to trigger the controlled rectifier device ofphase A;

e. eighth logic means coupled to the output of said second logic meansand to the output of said sixth logic means, the output of said eighthlogic means coupled to trigger the controlled rectifier device of phaseB; and

f. ninth logic means coupled to the output of said third logic means andto the output of said fourth logic means, the output of said ninth logicmeans coupled to trigger the controlled rectifier device of phase C.

4. The circuit of claim 3 further comprising means for enabling saidfourth, fifth and sixth logic means and disabling said first, second andthird logic means in response to a run signal.

5. The circuit of claim 4 further comprising means for enabling saidfirst, second and third logic means and disabling said fourth, fifth andsixth logic means in response to the first-occurring trailing edge.

1. 1An on-off duty cycle control circuit for an electrical devicepowered by a d.c. voltage supply derived from a threephase a.c. voltagesource through three-element controlled rectifier devices each of whichhas an anode connected to one of said three-phase voltages, said circuitcomprising: a. means generating a two level signal indicative of theon-off state of the electrical device to be controlled, b. meansgenerating a second signal of a magnitude indicative of the desiredon-off duty cycle of said electrical device, c. means receiving said twolevel signal and said second signal and generating therefrom a summedsignal, d. means receiving said summed signal and generating anintegrated summed signal, e. means receiving said integrated summedsignal and generating in dependence of the magnitude and slope of saidintegrated summed signal a control signal of a first magnitude for an''''on'''' period and of a second magnitude for the ''''off'''' periodof said desired duty cycle, f. means receiving said control signal andvoltages from each of the three phases of said a.c. source andgenerating during said ''''on'''' period three series of trigger pulses,each of said series for application to the control electrode of adifferent one of said controlled rectifier devices, each of said triggerpulses being timed to occur when the phase voltage of the anode of thecontrolled rectifier to which said trigger pulse is to be appliedbecomes the most positive of the three phase voltages of said a.c.source.
 2. A control circuit as defined in claim 1 wherein said lastnamed means further includes means generating an initial trigger pulseduring each of said ''''on'''' periods for application to the controlelectrode of the one of said controlled rectifiers whose anode was atthe reference voltage of said a.c. source at the beginning of said''''on'''' period, said initial trigger pulse being timed to occur assaid anode becomes more positive than said reference voltage.
 3. In anon-off duty cycle control circuit for an electrical device powered by ad.c. power supply derived from a a.c. source having phase voltage A, Band C through three-element controlled rectifier devices, each of whichhas an anode connected to one of said phase voltages, a logic circuitfor triggering said controlled rectifier devices comprising: a. first,second and third comparator means, said first comparator means havingphases A and C as inputs, said second comparator means having phases Aand B as inputs and said third comparator means having phases B and C asinputs, the output of each of said comparator means being a square wavesignal having leading edges and trailing edges; b. first, second andthird logic means having an enable input and coupled to be responsive toleading edges of, respectively, the first, second and third square wavesignals; c. fourth, fifth and sixth logic means having an enable inputand coupled to be responsive to trailing edges of, respectively, thefirst, second and third square wave signals; d. seventh logic meanscoupled to the output of said first logic means and to the output ofsaid fifth logic means, the output of said seventh logic means beingcoupled to trigger the controlled rectifier device of phase A; e. eighthlogic means coupled to the output of said second logic means and to theoutput of said sixth logic means, the output of said eighth logic meanscoupled to trigger the controlled rectifier device of phase B; and f.ninth logic means coupled to the output of said third logic means and tothe output of said fourth logic means, the output of said ninth logicmeans coupled to trigger the controlled rectifier device of phase C. 4.The circuit of claim 3 further comprising means for enabling saidfourth, fifth and sixth logic means and disabling said first, second andthird logic means in response to a run signal.
 5. The circuit of claim 4further comprisiNg means for enabling said first, second and third logicmeans and disabling said fourth, fifth and sixth logic means in responseto the first-occurring trailing edge.